Technology
Computation that happens in the memory, not next to it
A memristor stores a value as a physical resistance. Arrange millions of them in a grid and the grid performs a matrix multiplication by itself. That is the whole architecture, the rest is engineering.
The weight never moves
Storage and arithmetic happen in the same physical component, so there is nothing to fetch and nothing to write back.
A layer resolves in one step
Apply a voltage and the array settles to the answer, instead of working through millions of trips to memory to reach the same result.
Your PyTorch model, mapped
Export, compile, simulate against calibrated device models, then run. The same toolchain our own engineers use.
The wall
AI got bigger. The machine underneath it did not change.
Almost every processor in the world is built the same way: memory on one side, arithmetic on the other, and a bus in between. For a neural network, which is mostly one enormous multiply-accumulate, that bus is the whole problem. The energy is not spent computing. It is spent moving weights back and forth.
Moving a number from DRAM into a compute unit costs orders of magnitude more energy than the multiplication it feeds. Scale that to billions of parameters, several hundred times a second, inside a car or a drone or an implant, and the architecture runs out of budget long before the model runs out of accuracy.
“AI adoption worldwide is at five or six percent, and we already do not have enough energy. By the time we reach fifty percent, there is simply nowhere left to take that energy from.”
Mihai Raneti · Founder & CEO, CyberSwarm
The grid you can see is the array itself. Every crossing in it is one cell, and that cell both holds a weight and computes with it, which is why nothing has to travel for the arithmetic to happen.
See the lab it came out ofThe architecture
Four layers, from the material up
Pick the one you need. Each is self-contained, the device explains itself without the array, and the array without the fabric.
A component that remembers what current went through it
A memristor is a two-terminal element whose resistance changes with the charge that has passed through it, and stays changed when the power is removed. That resistance is a stored value and a physical multiplier at the same time. It is the closest thing electronics has to a synapse.
- Non-volatile: the weight survives power-down, so there is no reload cost at wake-up
- Analogue: many stable conductance levels per cell, not a single bit
- Dense: a passive element at the crossing of two wires, with no transistor per weight required
- CyberSwarm builds its elements from an IGZO resistive layer, programmed and read through planar contacts
“We store the same way we process.”
Side by side
Von Neumann versus in-memory compute
Not a benchmark, a structural comparison. The two architectures spend their energy on different things.
| Dimension | Conventional processor | CyberSwarm crossbar |
|---|---|---|
| Where computation happens | In an ALU, after the data arrives | In the memory cell itself |
| Cost of a matrix-vector product | O(n²) clocked MAC operations | One analogue settling step |
| Dominant energy cost | Moving weights across the memory bus | Cell current during the read pulse |
| Behaviour when idle | Clocked; leakage continues | Event-driven; near-zero between spikes |
| Weight storage | Volatile SRAM/DRAM, reloaded on wake | Non-volatile in the array, instant wake |
| Failure mode | A fault in the datapath is fatal | A degraded cell is a local precision loss |
| Data leaving the device | Typically offloaded to a cloud accelerator | Never. Inference is local by construction |
The toolchain
From a PyTorch checkpoint to running silicon
Novel hardware fails commercially when nobody can deploy to it. The stack was built alongside the device for exactly that reason.
01
Train where you already train
Bring a PyTorch model. Hardware-aware layers stand in for the analogue ones during fine-tuning, so the network learns to tolerate the noise, drift and quantisation it will meet on silicon.
02
Compile to the fabric
The compiler partitions the graph, quantises weights to achievable conductance levels, tiles each layer across physical arrays and emits a deployable binary with its calibration data.
03
Validate against a calibrated device model
Before silicon, the simulator replays the mapped model with measured device behaviour. Programming noise, conductance drift, IR-drop along the lines, stuck cells and ageing.
04
Deploy and keep it honest
The runtime executes on the engine and monitors it in the field: per-tile health, drift compensation and on-line re-calibration, with energy and latency reported per inference.
Engine
Reference-design characteristics
| Parameter | Value | Basis |
|---|---|---|
| Cell technology | IGZO thin-film resistive synapse | Patented |
| Selector | IGZO thin-film transistor, 1T1R | Patented |
| Levels per cell | Multi-level analogue | Reference design |
| Array organisation | Tiled crossbars, event-routed | Reference design |
| Weight retention | Non-volatile, no refresh | Architectural |
| Cold-start latency | No weight reload required | Architectural |
| Host interface | SPI / I²C / MIPI sensor bridge | Reference design |
| Toolchain | PyTorch export, compiler, runtime, simulator | Available to partners |
| Optical property | Transparent array, display-integrable | Patented |
Rows marked “reference design” are architectural targets used for partner scoping, not measured production silicon. Characterisation data for a specific configuration is shared under NDA during an evaluation.
A layer, as programmed into a tile
Try it against your model
How a layer falls onto the array
Give it the shape of a layer and it works out how much array that occupies. Geometry only, and it says so.
16 tiles 4 across by 4 down
- Cells provisioned
- 1,048,576
- Weights held
- 1,048,576
- Array utilisation
- 100%
Geometry only. This is how a dense layer falls onto tiles of the size you picked, and nothing more: it says nothing about throughput, latency or power, which depend on the configuration, the process and the workload. Those numbers come out of an evaluation against our device simulator, with your model, not out of a form.
Intellectual property
The architecture is protected at every layer it is built from
The portfolio does not start at a block diagram. It starts at how a resistive state is written into an IGZO thin film, and runs up through the crossbar array to a neural network whose weights and thresholds are both set in hardware. Full register, each filing linked to its own specification and its legal status checked against the register.
Open the patent register- 12
- Granted patents
- 4
- Under examination
- 2018
- Earliest priority
Straight answers
The questions engineers actually ask
Bring a model. We will tell you if it maps.
An evaluation starts with your workload profiled against our calibrated device simulator, including when the honest answer is that this is not the right architecture for it.