Intellectual property

A portfolio that starts at the material

It does not begin at an architecture diagram. It begins with how a resistive state is written into an IGZO thin film, and continues, layer by layer, up to a neural network whose thresholds and weights are both set in hardware.

12
Granted patents

United States and Europe

4
Published applications

Currently pending

9
Further publications

Pre-grant and lapsed, listed in full

2018
Earliest priority date

Terms running to 2039–2041

Public reporting describes the portfolio as 30+ patents; that figure also counts counterparts filed in Japan, Taiwan and under the PCT, which are not listed individually here. Everything else is: all 25 US and European filings on the public record, including pre-grant publications and the two applications that lapsed. Legal status was verified against the register in August 2026. Every patent shown as granted is in force with maintenance fees current.

Cornerstones

The three filings that define the architecture

One for the material, one for the array built from it, one for the network built from those. Everything else in the portfolio extends or defends these.

US 12,437,809 B2

Granted

United States
Granted 7 October 2025 · active, term to 2039

Programmable resistive memory element and a method of making the same

The device patent underneath everything else. A planar IGZO resistive element with both contacts in the same plane, programmed by localised thermal treatment through voltage sweeps and read non-destructively with a low-voltage pulse.

Inventors: Viorel-Georgel Dumitru, Cristina Besleaga Stan, Alin Velea, Aurelian-Cătălin Galca

US 12,069,870 B2

Granted

United States
Granted 20 August 2024 · active, term to 2039

Synapse array

The crossbar patent. IGZO thin-film transistors combined with IGZO resistive synapses, each holding an established resistance value. The array can be made fully transparent and integrated into the display of a portable device.

Inventors: Viorel-Georgel Dumitru, Cristina Besleaga Stan, Alin Velea, Aurelian-Cătălin Galca

US 2024/0428058 A1

Pending

United States
Under examination · published 26 December 2024 · also filed as WO 2024/263436

Hardware-based neural network and method of training

Layers of artificial neurons whose activation thresholds are adjusted electronically, with memristors providing the weighted connections between them, both the thresholds and the weights are set during training.

Inventors: Andrei Iliescu, Elena-Adelina Duca, Viorel-Georgel Dumitru

The register

Full filings

Every US and European filing on the public record, live or not, each linked to its own specification. Grants first, then applications under examination, then the pre-grant publications and the two that lapsed.

  • US 12,437,809 B2

    Granted

    Programmable resistive memory element and a method of making the same

    The device patent underneath everything else. A planar IGZO resistive element with both contacts in the same plane, programmed by localised thermal treatment through voltage sweeps and read non-destructively with a low-voltage pulse.

    The device · United States · Granted 7 October 2025 · active, term to 2039

    Google Patents
  • US 12,069,870 B2

    Granted

    Synapse array

    The crossbar patent. IGZO thin-film transistors combined with IGZO resistive synapses, each holding an established resistance value. The array can be made fully transparent and integrated into the display of a portable device.

    The array · United States · Granted 20 August 2024 · active, term to 2039

    Google Patents
  • EP 3588594 B1

    Granted

    Programmable resistive memory element and a method of making the same

    The European grant on the core device, maintained across Germany, France, Italy, the Netherlands, the Nordics and the Baltics among others. Those are the jurisdictions where the automotive and industrial customers are.

    The device · European Patent Office · Granted 24 January 2024 · in force in 17 states, term to 2039

    Google Patents
  • US 11,705,198 B2

    Granted

    Programmable resistive memory element and a method of making the same

    Continuation covering the voltage generator coupled to the coplanar contacts, applying thermal treatment to set the element’s resistance.

    The device · United States · Granted 18 July 2023 · active

    Google Patents
  • US 11,460,427 B2

    Granted

    Chemiresistor humidity sensor and fabrication method thereof

    A polyaniline emeraldine doped with sulfonated nanocellulose, electrospun onto interdigitated electrodes as the sensing layer of a chemiresistive humidity sensor.

    Sensing materials · United States · Granted 4 October 2022 · active, term to 2041

    Google Patents
  • US 11,455,258 B2

    Granted

    Method and system for data validation using memristors

    Encryption keys generated independently on two devices without the key ever being transmitted: identical setting and reading voltages applied to matched memristors yield the same character string at both ends, with the parameters sent over a second channel.

    Secure edge systems · United States · Granted 27 September 2022 · active, term to 2040

    Google Patents
  • US 11,386,953 B2

    Granted

    Multiple memory states device and method of making same

    The phase-change variant: a resistive layer between two contacts, thermally treated after fabrication to initiate crystallisation and open up a large number of stable resistance states.

    The device · United States · Granted 12 July 2022 · active, term to 2039

    Google Patents
  • US 11,356,422 B2

    Granted

    Secure communication system and method

    Generalises the key-agreement scheme to any device with non-linear I-V characteristics, a physical unclonable function on both the sender and the receiver side.

    Secure edge systems · United States · Granted 7 June 2022 · active, term to 2040

    Google Patents

Families

How the portfolio is organised

The device

How a resistive state is written into an IGZO thin film and read back without disturbing it. This is the layer nobody can design around by writing better software.

The array

Crossbar organisation: thin-film transistors selecting resistive synapses, in a structure transparent enough to sit behind a display.

The computation

Turning a passive matrix of conductances into a machine that classifies. Artificial neurons, trainable thresholds, and recognition built from paired arrays.

Secure edge systems

Protecting the device and the traffic around it, including key generation that exploits the physical variability of memristors rather than a stored secret.

Strategy

Why it is shaped this way

The portfolio is vertical, not defensive

It starts at the material and ends at a trainable network. Owning the device and the array together is what allows the compiler to assume behaviour a fabless competitor would have to negotiate with a foundry.

Priority dates from 2018, still being extended

The founding filings predate the current wave of interest in analogue in-memory compute. Five US patents now continue from the first device application, the most recent filed in September 2025, and the granted terms run to between 2039 and 2041.

Filed by the people who built it

The core patents name the company’s own device physicists and materials scientists. The IP and the lab are the same effort, not an acquisition.

Licensing enquiries are welcome.

The engine can be licensed as IP into a partner’s own silicon. Freedom-to-operate discussions start with the commercial team.