Your training pipeline stays yours
We plug in at the deployment end, not the training end. Your data, your framework, your MLOps and your model ownership are untouched. Nothing has to move to us for this to work.
Partner programme
Novel silicon fails commercially when nobody can deploy to it. The toolchain was built alongside the device so that adopting this architecture is an engineering decision, not an act of faith.
We plug in at the deployment end, not the training end. Your data, your framework, your MLOps and your model ownership are untouched. Nothing has to move to us for this to work.
We publish the accuracy envelope we measure, including when it says your workload is a poor fit. A fast no costs both sides far less than a slow maybe.
Device physics, array architecture and compiler are developed in the same building. When behaviour surprises you, the answer comes from the people who characterised the silicon, not from a vendor negotiating with a foundry.
The same architecture ships either as silicon you design in, or as IP you integrate into your own. The commercial shape follows your programme, not ours.
Application domains
Six domains, one shared constraint: the inference has to complete on the device, inside a fixed power budget, without a network round-trip.
Automotive
Sensor fusion, driver monitoring and predictive diagnostics that run inside the ECU on a power budget a vehicle can actually spare, with a wake-up that costs nothing, because the weights never left the array.
Aerospace & Defence
On-board processing for airborne and orbital systems where the downlink is narrow, contested or absent, and where a single-event upset must degrade the answer, not end the mission.
Robotics & Physical AI
Reflex-rate perception and control for manipulators, mobile robots and drones, where a decision that arrives 200 ms late is not a decision at all.
Healthcare & Medical Devices
Wearable and implantable devices that classify physiological signals on the device, where privacy is a property of the architecture rather than a clause in a policy document.
Industrial & Energy
Retrofit intelligence for factory floors, grid assets and remote infrastructure. Nodes that run for years on a harvested or battery supply and report an event, not a stream.
Consumer & IoT
Wake-word, presence, gesture and context awareness that stay on continuously without the power draw or the privacy cost. Because the array is transparent, it can sit behind the display.
Not listed? If the workload is dominated by matrix-vector products and cannot depend on a network, it fits the same shape whatever the industry is called. See the full breakdown per industry.
How we work together
Each stage is designed to be exited cheaply. You should be able to walk away after an evaluation with a clear answer and no sunk platform commitment.
Teams assessing feasibility
Establish whether your workload maps well before anyone commits budget. We profile your model against the calibrated device simulator and give you an honest answer, including when the answer is no.
Partners building a product
Co-development against a reference design. Your engineers get the full toolchain, hardware to develop on, and direct access to the people who built the compiler.
Programmes heading to production
Production engagement with qualification support, supply commitments and a roadmap you are allowed to plan against.
What you get
PyTorch-compatible layers. Linear, Conv2d, attention and spiking blocks, so hardware-aware fine-tuning happens inside your existing training code rather than beside it.
Partitions the graph, quantises to achievable conductance levels, tiles layers across physical arrays and emits a deployable binary with its calibration data.
Replays the mapped model against measured device behaviour: programming noise, drift, IR-drop along the lines, stuck cells and ageing. You see the accuracy envelope before committing.
Executes on the engine and monitors it in the field. Per-tile health, drift compensation, on-line re-calibration, and energy and latency reported per inference.
The path
The same four steps every integration follows.
01
Bring a PyTorch model. Hardware-aware layers stand in for the analogue ones during fine-tuning, so the network learns to tolerate the noise, drift and quantisation it will meet on silicon.
02
The compiler partitions the graph, quantises weights to achievable conductance levels, tiles each layer across physical arrays and emits a deployable binary with its calibration data.
03
Before silicon, the simulator replays the mapped model with measured device behaviour. Programming noise, conductance drift, IR-drop along the lines, stuck cells and ageing.
04
The runtime executes on the engine and monitors it in the field: per-tile health, drift compensation and on-line re-calibration, with energy and latency reported per inference.
Send us the workload and the constraints. We profile it against the calibrated simulator and come back with an accuracy envelope, an energy estimate and an honest verdict.